In various electronics industries, particularly the storage industry, serialized interconnects are becoming increasingly popular for use connecting root complexes to input/output (I/O) devices than parallel communications. Industry has found serialized communications to achieve better noise immunity and faster speeds. One popular serial communications interface is PCI Express or PCI-E. In a typical PCI-E system, a root complex interconnects a processor system (with one or more CPUs and memory) to various endpoints (e.g., I/O devices) over point-to-point serial connections, referred to as links. Each link has a width determined by its number of lanes. Each lane contains two pairs of wires: one pair for receiving low-voltage differential signals and the other pair for transmitting low-voltage differential signals.
To produce flexible, manufacturable, and serviceable products, some electronics enclosures (e.g., embedded storage arrays) implement the root complex and I/O devices on separate pluggable modules (i.e., as CPU modules and I/O modules, respectively). A given CPU module typically communicates with a set of I/O modules. Notwithstanding the flexibility provided by modularized CPUs and I/Os, the design of the midplane or backplane typically fixes the specific connectivity between the CPU modules and I/O modules.
Enterprises often offer families of electronics products ranging from low-end (e.g., low performance, low cost, low storage capacity) products to high-end (e.g., high performance, high cost, large storage capacity). To economize, an enterprise may offer a limited number of CPU module designs in support of its family of products, approaching a “one-size-fits-all” design policy. Often, however, such a policy can lead to unsatisfactory and unpopular compromises: in order to accommodate a wide variety of products, the “one-size-fits-all” CPU module usually includes components and functionality unused by some products. The unused components present unnecessary expense.
For example, one electronics product may need peer-to-peer communications between CPU modules, whereas another product has no need for such communications. To support the product with the peer-to-peer requirement, a single CPU module includes a protocol switch with a non-transparent port. Peer CPU modules communicate with each other through their non-transparent ports. For a product without this feature, this switch is an unnecessary additional cost.
As another example, a low-end product may have a requirement for a high degree of connectivity for its I/O modules. Accordingly, the CPU module employs a fan-out switch to increase the number of available lanes provided by the root complex and distribute such lanes to each of the I/O modules. Although this may enable any given I/O module to perform to its bandwidth capability, the overall effect of fan-out on the system can be to reduce performance. A high-end product, designed for high-speed operation, not only may find the fan-out switch unnecessary, but also an impediment to the product's performance. These examples thus illustrate that a single CPU module design, in general, cannot efficiently serve diverse products.